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Ultra Low Output Voltage Linear FET Controller
POWER MANAGEMENT Description
The SC339 is an ultra-low output voltage, linear power supply controller designed to simplify power management for notebook PCs. It is part of Semtech's Smart LDO TM family of products. The SC339 has a user adjustable output that can be set anywhere between 0.5V and 3.3V using two external resistors. SC339 features include tight output voltage regulation ( 1% over 0C to +85C), enable control, open drain power good signal, under-voltage protection and soft-start. The enable pin allows the part to enter a very low power standby mode. Pulling it high enables the output. The power good pin is an open drain and asserts low when the voltage at the adjust pin is below 88% (typ) of nominal. If the voltage at the adjust pin is below 50% (typ) of nominal, the undervoltage protection circuitry will shut down the output. The SC339 is available in a tiny SOT-23 6-pin surface mount package.
SC339
Features
1% Voltage Accuracy Over-Temperature Low Shutdown Current Runs Off 5V Supply Ultra-Fast Transient Response Enable Control for the Output Power Good Monitoring and Signaling for the Output Gate Drive from Input Supply Enables Use of N-Channel MOSFET User Selectable Dropout Voltage Under-Voltage Protection for the Output SOT-23 6-pin Surface Mount Package Compatible with Ceramic Capacitors Low Ripple Output Internal 1ms soft-start requires no external components Fully WEEE and RoHS compliant
Applications
Notebook PCs Desktop Computers Battery Powered Devices Portable Instruments
Typical Application Circuit
1.2V +/-5% IN
C1
IRF7311 or similar
Vout = (1+R1/R2)*0.5 1.05V @ 3A C2 5V IN R1
IN
DRV
GND SC339 ADJ 1.05V Enable EN PGD 1.05V Power Good
R3 (1)
C4
Notes: (1) Optional Components to use with ceramic output capacitors (C2)
R2 C3 (1)
Sept 11, 2006
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SC339
POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
Parameter Input Supply Voltage Drive Pin Adjust and Power Good Pin Enable Pin Thermal Impedance Junction to Ambient Thermal Impedance Junction to Case Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. ESD Rating (Human Body Model)
Symbol VIN VDRV VADJ, VPGD VEN JA JC TA TJ TSTG TLEAD VESD
Maximum -0.3 to +6 -0.3 to VIN + 0.3V -0.3 to VIN + 0.3V -0.3 to VIN + 0.3V 190 81 -40 to +85 -40 to +125 -65 to +150 300 2
Units V V V V C/W C/W C C C C kV
Electrical Characteristics
Unless specified: TA = 25C, VIN = VEN = 5V 5%, VPWR(1) = 1.5V 5%, 0A IOUT 3A. Values in bold apply over full operating ambient temperature range.
Parameter Supply Voltage Quiescent Current Standby Current Input Under-Voltage Lockout Start Threshold Hysteresis EN Enable Input Threshold
Symbol VIN IQ IQ(OFF)
Conditions
Min 4.5
Typ 5 130 0.1
Max 5.5 200 1.0
Units V A A
VIN = 5V EN low
VUVLO VHYST
VIN rising VIN falling
4.20 0.10
V V
VIH VIL
Output on Output off VIN = VEN = 5V
2.8 V 1.8 -1 +1 A
Enable Input Bias Current
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SC339
POWER MANAGEMENT Electrical Characteristics
Parameter ADJ Adjust Input Bias Current Reference Voltage DRV Sourcing Output Current IDRV Sinking Output Voltage Output Under-Voltage Protection Trip Threshold(2) PGD Power Good Threshold(3) Output Logic Low Voltage Power Good Leakage Current Soft-Start Output Rise Time 10% VOUT to 90% VOUT, VOUT = 1.05V tr From EN rising to 99% of VOUT 500 1000 2000 s VTH(PGD) VPGD IPGD Measured at ADJ pin VADJ = 0.4V, IPGD = -1mA VADJ = 0.5V, 0V VPGD VIN -1 0 -15 -12 -8 0.4 +1 %VADJ V A VTH(UV) Measured at ADJ pin 40 50 60 %VADJ VDRV Full On, IDRV = 0mA, VIN = 5V 5 4.70 20 4.85 mA V 5 20 mA IADJ VADJ VADJ = 0.5V 0C TA +85C -100 -1% 0 0.500 +100 1% nA V Symbol Conditions Min Typ Max Units
Notes: 1) VPWR = input voltage to pass device drain (or source depending upon orientation of FET). 2) If V TH(UV) is exceeded for longer than 1ms (nom.) the protection circuitry will shut down the output. 3) During start-up only, V TH(PGD) is -6% (typical), then switches to -12% (typical).
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SC339
POWER MANAGEMENT Pin Configuration
Top View
IN GND EN 1 2 3 6 5 4 DRV ADJ PGD
PRELIMINARY Ordering Information
Part Number SC339SKTRT SC339EVB Package SOT-23 6 Pin Evaluation Board
(SOT-23 6L)
Notes: 1) Only available in tape and reel packaging. A reel contains 2500 devices. 2) VIN = 5V 3) VADJ is 1% over 0C TA +85C. 4) Lead-free product. This product is fully WEEE and RoHS compliant.
Marking Information
Marking for SOT23, 6 lead package: yyww = Datecode (Example: E652)
Pin Descriptions
Pin 1 2 3 4 5 6 Pin Name IN GND EN PGD ADJ DRV Pin Function 5V supply Ground Active high enable control - connect to IN if not being used - do not allow to float Power good signal output for VOUT Regulator sense input - used for sensing the output voltage for power good and under-voltage and to set the output voltage Output of regulator - drives the gate of an N-channel MOSFET to maintain VOUT set by R1 and R2
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SC339
POWER MANAGEMENT Block Diagram
IN
0.5V Bandgap Reference
EN
Shutdown Control
Vref ( 0.5V)
DRV + Vref
Error Amplifier 0.5 VBG
ADJ
Under Voltage Control
+ -
Undervoltage Comparator
PGD + Power Good Comparator 0.88 VBG
(0.95 VBG At start-up)
GND
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SC339
POWER MANAGEMENT Applications Information
Theory Of Operation The SC339 linear FET controller provides a simple way to drive an N-channel MOSFET to produce tightly regulated output voltages from an available, higher, supply voltage. It takes its power from the 5V system supply, drawing 130A (typ) while operating. It contains an internal bandgap reference which is compared to the output voltage via a resistor divider. The resistor divider is external and user selectable. The drive pin (DRV) can pull up to a guaranteed minimum of 4.7V. Thus, the device can be used to regulate a large range of output voltages by careful selection of the external MOSFETs (see Component Selection on this page). The SC339 includes an active high enable control (EN). If this pin is pulled low, the drive pin is pulled low, turning off the N-channel MOSFET. If the pin is pulled up to 2.8V VEN VIN, the drive pin is enabled. This pin should not be allowed to float. The SC339 has a power good output (PGD) which is an open drain output that pulls low if the related output is below the power good threshold (-12% of the programmed output voltage typical). The power good circuitry is active if the device is enabled, regardless of the state of the over-current latch. An over-current protection circuit monitors the output voltage. If the output voltage drops below 50% (typical) of nominal, as would occur during an over-current or short condition, the device will pull the drive pin low and latch off. Toggle the power supply or enable pin to reset the latch condition. Drive Output The drive output is source and sink capable. The drivers both source and sink 20mA of current typically at 5V IN. Soft-Start and Power Good Timing At start-up, the internal reference is switched from its normal 0.5VDC to a 1ms (typical) linear ramp. The output voltage tracks the ramp until 0.5V is reached. The PWRGD signal is held low until the output has been in regulation approximately 500sec to allow the output voltage to
(c) 2006 Semtech Corp.
PRELIMINARY
stabilize. The power-up is very smooth and monotonic. OCP and Power Supply Sequencing The SC339 has output under-voltage protection that looks at the output to see if it is: a) less than 50% (typical) of its nominal value and, b) VDRV for that output is within 350mV (typical) of maximum. If both of these criteria are met, there is a 1ms (typical) delay and then the output is shut down. This provides inherent immunity to UV shutdown at start-up (which may occur while the output capacitors are being charged). At star t-up, it is necessar y to ensure the power supplies and enable are sequenced correctly to avoid erroneous latch-off. For UV latch-off not to occur at start-up due to sequencing issues, the voltage supplied to the MOSFET drain should be greater than the output under-voltage threshold when that output is enabled. This assumes that the drop through the pass MOSFET is negligible. If not, then this drop needs to be taken into account also since: VOUT = VDRAIN - (IOUT x RDS(ON)) If the supply to the SC339 IN pin comes up before the supply to the MOSFET drain, then that output should be enabled after the supply to the MOSFET drain is applied - the power good signal for this rail would be ideal. If the power supply to the MOSFET drain comes up before the power supply to the SC339 IN pin, then the output can either be enabled with the supply to the IN pin or afterwards. Please note the following example: SC339 powered from 5V, the MOSFET (VDRAIN) powered from 1.8V, set for 1.5VOUT. Worst-case: under-voltage threshold is 60% (over temperature) of 1.5V, or 0.9V. The typical enable threshold is ~2.4V, see Figure 1 on Page 7. Component Selection Output Capacitors: low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for bulk capacitance, with ceramic bypass capacitors for decoupling high frequency transients. Ceramic output capacitors may be used; however, use of ceramic output capacitors requires compensation on the DRV output.
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SC339
POWER MANAGEMENT Applications Information (Cont.)
Input Capacitors: placement of low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps at the input to the MOSFET (VDRAIN) will help to hold up the power supply during fast load changes, thus improving overall transient response. If VDRAIN is located at the bulk capacitors for the upstream voltage regulator, additional capacitance may not be required. In this case a 0.1F ceramic capacitor will suffice. The 5V bias supply to the SC339 should be bypassed with a 0.1F ceramic capacitor. MOSFETs: ver y low or low threshold N-channel MOSFETs are required. Select FETs rated for V GS of 2.7V or lower. For the device to work under all operating conditions, a maximum RDS(ON) must be met to ensure that the output will never go into dropout: VIN(MIN) VOUT(MAX) RDSON(MAX) = -------------- IOUT(MAX)
Note: RDS(ON) must be met at all temperatures and at the minimum VGS condition.
Setting The Output Voltage: the adjust pin connects directly to the inverting input of the error amplifier, and the output voltage is set using external resistors (please refer to the Typical Application Circuit on Page 1). Using output 1 as an example, the output voltage can be calculated as follows: R1 VOUT = 0.5 * ( 1 + ---- ) R2 The input bias current for the adjust pin is so low that it can be safely ignored. To avoid picking up noise, it is recommended that the total resistance of the feedback chain be less than 100k. With ceramic capacitors, a recommended divider current of >100A is recommended to keep the FET conducting during light load conditions to improve transient response.
2.8V
SC339 Supply Comes Up Before MOSFET Drain Supply
2.7V
MOSFET Drain Supply Comes Up Before SC339 Supply
Power Supply Sequencing
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SC339
POWER MANAGEMENT Applications Information (Cont.)
Table 1 lists recommended resistor values for some standard output voltages. All resistors are 1%, 1/10W. The maximum output voltage that can be obtained from each output is determined by the input supply voltage and the RDS(ON) and gate threshold voltage of the external MOSFET. Assuming that the MOSFET gate threshold voltage is sufficiently low for the output voltage chosen and the worst-case drive voltage, VOUT(MAX) is given by: VOUT (MAX) = VDRAIN(MIN) IOUT(MAX) * RDSON(MAX)
VOUT (V) 1.05 1.2 1.5 2.5 3.3 R1 or R3 (k) 11.0 14.0 20.0 45.3 63.4 R2 or R4 (k) 10.0 10.0 10.0 11.3 11.3
PRELIMINARY
Total DC error = 2.25% = 23.6mV This leaves 2.75% = 28.875mV for the load transient ESR spike, therefore: 28.875mV RESR(MAX) = ------------ = 11.55m 2.5A Bulk capacitance required is given by: dl * CBULK(MIN) = ------ = F dV Where dI is the maximum load current step, t is the maximum regulator response time and dV is the allowable voltage droop. Therefore with dI = 2.5A, t = 1s, and dV = 28.875mV: 2.5 * 1 * 10 CBULK(MIN) = ---------------- = 87F 3 28.875 * 10 So if we use 1% VOUT set resistors we would select 100F, 12m POSCAP for output capacitance (which assumes that local ceramic bypass capacitors will absorb the balance of the (12 - 11.55)m ESR requirement - otherwise 10m capacitors should be used). If we use 0.1% set resistors, then the total DC error becomes 1.35% = 15.75mV, leaving 3.65% = 38.33mV for the ESR spike. In this case: 38.33mV RESR(MAX) = -------- = 15.33m 2.5A
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Recommended Resistor Values For SC339 Design Example Goal: 1.05V5% @ up to 2.5A from 1.2V5% and 5V5% Solution 1: No Passive Droop Total window for DC error, ripple and transient is 52.5mV. Since this device is linear and assuming that it has been designed to not ever enter dropout, there is negligible ripple on the output. The DC error for this output is the sum of: VADJ accuracy = 1% = 10.5mV Feedback chain tolerance = 1% = 10.5mV Load regulation = 0.25% = 2.6mV Resistors per Table 1 should be 11.0k (top) and 10.0k (bottom).
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and,
2.5 * 1 * 10 CBULK(MIN) = -------------- = 65F 3 38.33 * 10 So for 0.1% resistors we could use 1 x 100F, 15m POSCAP for output capacitance.
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SC339
POWER MANAGEMENT Applications Information (Cont.)
This is a ver y severe example, since the output voltage is so low, therefore the allowable window is ver y small. See Solution 2 for an alternate circuit. For higher output voltages the components required will be less stringent. The input capacitance needs to be large enough to stop the input supply from collapsing below -5% (i.e., the design minimum) during output load steps. If the input to the pass MOSFET is not local to the supply bulk capacitance then additional bulk capacitance may be required. MOSFET selection: since the input voltage to the SC339 is 5V5%, the minimum available gate drive is: VGS = (4.4 1.1025) = 3.3V So a MOSFET rated for VGS = 2.7V will be required, with an RDS(ON)(MAX) (over-temperature) given by: (VIN(MIN) VOUT ) (1.14 1.05) RDSON(MAX) = ------------ = ------------ = 36m IOUT(MAX) 2.5 MOSFET SELECTION SO-8 Footprint FDS6682 IRF7456 1206 Footprint Si5406DC NTHS5404 SOT-23 Footprint IRLMS2002 FDN337N (when Input is > 1.2V for 1.05V output) Vgs 1.7V 1.5V Vgs 0.6V 0.6V Vgs 1V 0.7V Rds-on 9m 6.5m Rds-on 20m 25m Rds-on 30m 65m Imax 14A 16A Imax 9.5A 7.2A Imax 5.2A 2.2A Solution 2: Using Passive Droop
1.2V +/-5% IN C1 0.1uF RDROOP 1.05V @ 2.5A C3 20mOhm 1.075V Q1
R1 100uF, 25mOhm POSCAP 11.0k 4 5 6 R2 10.0k
U1
PGD ADJ DRV
SC339
EN GND IN
3 2 1
Passive droop allows us to use almost the full output tolerance window for transients, therefore making the o u t p u t c a p a c i to r s e l e c t i o n s i m p l e r a n d l e s s expensive. The trade-offs are the cost of the droop resistor versus the reduction in output capacitor cost, and the reduction in headroom which impacts MOSFET selection. The top of the feedback chain connects to the input side of RDROOP, and the output is set for 1.075V. Thus at no load, VOUT will be 1.075V (or 1.05V + 2.4%) and at IOUT = 2.5A, VOUT will be 1.025V (or 1.05V - 2.4%). If 1% set resistors are used, the total DC error will be 2.25% = 24mV. Thus, at no load, the minimum output voltage will be given by: VOUT(MIN_NO_LOAD) = 1.075 0.024 = 1.051V This leaves 53.5mV for transient response, giving: 53.5mV RESR(MAX) = -------- = 21.4m and, 2.5A 2.5 * 1 * 10 CBULK(MIN) = -------------- = 47F 53.5 *103 Instead of 2 x 100F, 12m capacitors, we can use 1 x 47F, 15m capacitor.
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SC339
POWER MANAGEMENT Applications Information (Cont.)
Using Ceramic Capacitors SC339 is capable of operation using an all-ceramic solution, needing only an external R-C compensation. The Typical Application schematic (R3, C3) from page 1 is reproduced here:
1.2 V +/-5 % IN IRF7311 or similar
PRELIMINARY
From this response we see that the system is not stable as it has a phase margin of approximately 0 degrees. For stable operation we introduce a low frequency pole and a zero. The low frequency pole is used to roll off the gain quicker and the zero is used to increase the bandwidth of the system.
C1
V out = (1+R1/R2)*0.5 1.05 V @ 3A C2 5 V IN R1
The Pole-Zero location:
Gain (dB) PHASE (deg)
IN GND 1.05V Enable EN
DRV
60 Pin + Pcomp
270
SC339 ADJ
PGD 1.05 V Power Good
40
R 3 (1)
Ceramic Capacitor Operation with Compensation on DRV pin
180
C4
Notes : (1 ) Optional Components to use with ceramic output capacitors (C2)
R2 C 3 (1)
20 Prout Zin + Zcomp Pcout 1K 10K 100K 1MEG 10MEG
90
0,0
100
FREQ (Hz)
Typical Applications Circuit
-20
PHASE
-90
-40
-180
Typical Frequency Response without Compensation and Ceramic Output Capacitors:
Gain (dB) Low frequency pole generated internally 60 Pin Low frequency zero generated internally Zin 40 Prout Rout / Cout pole, moves with the load current 180 270 PHASE (deg)
-60
-270
SC339 Frequency Response with Ceramic Output Capacitors and R-C Compensation
20 Pcout
High frequency pole generated by ESR and Output Capacitor
90
0,0
100
1K
10K
100K
1MEG
10MEG
FREQ (Hz)
From the above figure we can see that the overall response of the system is stable with a decent phase margin It is important to select the external compensation zero to be between 1 kHz and 5 kHz for optimum bandwidth and phase margin. In this example we have selected zero at approximately 3 kHz. The compensation values are calculated by the following empirical equation: 1/2* * R3 * C3 = 3kHz We chose a low R3 compensation value to roll off gain. R3 = 100 .
PHASE -20 -90
-40
Ceramic Capacitor operation with very low ESR for the output capacitor . We get a three pole 1 zero system as shown above and is unstable without external compensation
-180
-60
-270
SC339 Frequency Response with Ceramic Output Capacitors and no Compensation
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SC339
POWER MANAGEMENT Applications Information (Cont.)
Now, C3 = 1/2 * * R3 * 3kHz = 530nF We choose C3 = 470nF as the standard value. Soft-Start Behavior At start-up, VOUT first ramps linearly from ground at the rate of ~0.5V/ms (+/- 25%) for about 800us. The linear ramping is followed by a phase of smooth settling for about 700us at the end of which the output has fully settled (to better than 1%). The total start-up time of about 1.5ms is kept within 1ms - 2ms window, and this is regardless of the loading and of the external components connected to the device. Layout Guidelines The advantages of using the SC339 to drive external MOSFETs are: a) that the bandgap reference and control circuitry are in a die that does not contain high power dissipating devices and, b) that the device itself does not need to be located right next to the power devices. Thus very accurate output voltages can be obtained since changes due to heating effects will be minimal. The 0.1F bypass capacitor should be located close to the supply (IN) and GND pins, and connected directly to the ground plane. The feedback resistors should be located at the device, with the sense line from the output routed from the load (or top end of the droop resistor if passive droop is being used) directly to the feedback chain. If passive droop is being used, the droop resistor should be located next to the load to avoid adding additional unplanned droop. Sense and drive lines should be routed away from noisy traces or components. For very low input to output voltage differentials, the input to output/load path should be as wide and short as possible. Where greater headroom is available, wide traces may suffice. Power dissipation within the device is practically negligible, thus requiring no special consideration during layout. The MOSFET pass devices should be laid out according to the manufacturer's guidelines for the power being dissipated within them.
SC339 Start-Up Response
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SC339
POWER MANAGEMENT Performance Characteristics
Supply Current vs. Supply Voltage
VCC = 4.5V to 5.5V, IOUT = 2.5A, VIN = 1.5V, VEN = 5V 160.0E-6 155.0E-6 150.0E-6
PRELIMINARY
Adjust Voltage vs. Output Current
IOUT = 0A to 3A, VIN = 1.5V, VCC = 5.0V, VEN = 5V 0.5060 0.5040 0.5020
I CC (A)
VADJ (V)
4.600 4.700 4.800 4.900 5.000 VCC (V) Supply Current 5.100 5.200 5.300 5.400 5.500
145.0E-6 140.0E-6 135.0E-6 130.0E-6 125.0E-6 4.500
0.5000 0.4980 0.4960 0.4940 0.000
0.500
1.000
1.500 IOUT (A)
2.000
2.500
3.000
Adjust Voltage
+1%
-1%
Figure 1: Supply Current v/s Supply Voltage Figure 2: Adjust Voltage v/s Output Current (1% accurate)
Figure 3: Soft Start waveform shows the PWRGD delay
Figure 4: Input UVLO Test (Rising)
Figure 5: Input UVLO Test (Falling)
Figure 6: Enable threshold detect (Rising)
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SC339
POWER MANAGEMENT Performance Characteristics
Figure 7: Enable threshold detect (Falling)
Figure 8: Transient load rising edge
Figure 9: Transient load falling edge
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SC339
POWER MANAGEMENT Outline Drawing - SOT-23 6 PRELIMINARY
A e1 N EI 1 ccc C 2X N/2 TIPS B 2 E D
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b c D E1 E e e1 L L1 N 01 aaa bbb ccc .057 .035 .006 .000 .035 .045 .051 .020 .010 .009 .003 .110 .114 .118 .060 .063 .069 .110 BSC .037 BSC .075 BSC .012 .018 .024 (.024) 6 10 0 .004 .008 .008 1.45 0.90 0.00 0.15 .90 1.15 1.30 0.25 0.50 0.22 0.08 2.80 2.90 3.00 1.50 1.60 1.75 2.80 BSC 0.95 BSC 1.90 BSC 0.30 0.45 0.60 (0.60) 6 0 10 0.10 0.20 0.20
2X E/2
e
D aaa C A2 SEATING PLANE C A1 bxN bbb C A-B D A
H GAGE PLANE 0.25
H c
L (L1)
01
SEE DETAIL SIDE VIEW
NOTES: 1. 2. 3.
A
DETAIL
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -HDIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
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SC339
POWER MANAGEMENT Land Pattern - SOT-23 6
X
DIM
(C) G Y P Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.098) .055 .037 .024 .043 .141 (2.50) 1.40 0.95 0.60 1.10 3.60
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
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